1. Technical Field
The present disclosure generally relates to carbon nanotube field effect transistor (CNTFET) devices. The present disclosure also generally relates to device structures and methods for providing CNTFET devices with enhanced current carrying capability at lower densities.
2. Discussion of Related Art
Any discussion of the related art throughout this specification should in no way be considered as an admission that such art is widely known or forms part of the common general knowledge in the field.
Static electricity is generated when objects obtain electrostatic charges through contact and separation of the objects that causes a transfer of electrons between the objects. The transfer of electrons is determined by the type of contact and separation between the objects, such as rubbing, brushing, or wiping for example, and the properties of the materials of the objects. The transfer of electrons occurs when electrons on the surface of an object are relocated to the surface of another object and the transfer of electrons creates electrostatic charges on the objects. The object that donates electrons obtains a positive electrostatic charge and the object that captures electrons obtains a negative electrostatic charge. The positive electrostatically charged object can cause an electrostatic discharge event when the positive electrostatically charged object is rapidly discharged and the negative electrostatically charged object can cause an electrostatic discharge event when the negative electrostatically charged object is rapidly discharged. The positive electrostatically charged object and the negative electrostatically charged object can be rapidly discharged though direct contact or indirect contact with an object that allows for rapid discharge.
The human body frequently obtains an electrostatic charge through common daily activities, such as walking on carpet, ascending from a fabric covered seat, and removing clothing for example, that cause a transfer of electrons between the human body and other objects. The human body model (HBM) was developed to simulate an electrostatic discharge event caused by the electrostatically charged human body contacting an object that allows for rapid discharge. The human body model uses a HBM circuit 105 shown in prior art FIG. 1A and an ESD current 150 shown in prior art FIG. 1B for calculating the strength of an electrostatic discharge event caused by the electrostatically charged human body. The HBM circuit 105 has a 100 pF capacitor C that discharges through a 1,500 Ohm series resistor R and a switch 107 to the object that allows for rapid discharge. Prior art FIG. 1A illustrates circuit 100 having the HBM circuit 105 electrically connected to an on-chip circuit 110 that receives an ESD current and voltage discharge from the HBM circuit 105. The contact between HBM circuit 105 and pads 120 and 125 associated with the on-chip circuit 110 is shown symbolically by switch 107 transitioning from an open position to a closed position. Pads 120 and 125 may be input pads, output pads, input/output pads, power supply, or ground pads for example. The terms connected, coupled, electrically connected, and electrically coupled are used interchangeably in this disclosure and the terms refer to a connection that allows electrical signals to flow either directly or indirectly from one component to another. The direct flow of electrical signals from one component to another does not preclude intervening passive devices that do not generate electric energy such as resistors, capacitors, and inductors. The indirect flow of electrical signals from one component to another does not preclude intervening active devices such as transistors or flow of electrical signals by electromagnetic induction.
An electrostatic charge stored on the 100 pF capacitor C produces a voltage VCHARGE that is discharged when HBM circuit 105 comes into contact with pads 120 and 125 associated with the on-chip circuit 110. The electrostatic charge is discharged from capacitor C and flows through the 1,500 Ohm series resistor R, switch 107 in a closed position, and into pads 120 and 125 at a rate determined by ESD current source (IESD) 115. The rate of ESD current flow as a function of time, during an ESD discharge based on the human body model HBM 105, is given by ESD current 150 illustrated in prior art FIG. 1B. The ESD current 150 reaches a peak current of 1 Ampere after 10 ns, then drops to 0.5 Amperes after 115 ns, then to 0.37 Amperes (37% of the peak current value) after 180 ns, and then discharges to zero current. ESD current 150 is not defined beyond 180 ns and ESD current 150 beyond 180 ns is not needed to determine the maximum VESD induced across the pads 120 and 125. The ESD current source 115 approximates an ideal current source in which ESD current 150 is independent of the voltage VESD that is induced between pads 120 and 125 by ESD current 150. Therefore, circuit elements in circuit 100 determine the maximum VESD during an ESD event instead of the ESD current source 115 that delivers ESD current 150 independent of voltages that may appear across the terminals of ESD current source 115.
The on-chip circuit 110 includes an ESD protect circuit 130 that is electrically connected in parallel with pads 120 and 125 by nodes 126 and 127 and a protected circuit 140 that is electrically connected in parallel with pads 120 and 125 by nodes 128 and 129. The term node refers to a point of connection or junction where conductors and/or components meet. The ESD protect circuit 130 is designed to protect the protected circuit 140 from being damaged by ESD-driven (induced) voltage surges during handling of the on-chip circuit 110. The ESD protect circuit 130 is traditionally constructed from semiconductor diodes that create conducting paths for dissipating the positive and negative ESD-driven voltages. The semiconductor diodes are used in pairs with a first semiconductor diode for creating a conducting path to limit ESD-voltage surges of a positive polarity to an acceptable value and a second semiconductor diode for creating a conducting path to limit ESD-voltage surges of a negative polarity to an acceptable value. The acceptable values are selected such that the protected circuit 140 will not be damaged by ESD-driven voltages and the acceptable values may be selected based on characteristics of the protected circuit 140. For example, the protected circuit 140 may be constructed from metal oxide semiconductor field effect transistors (MOSFETs) and the acceptable values are selected based on the dielectric breakdown strength of the MOSFETs' gate insulators. However, a circuit designer can select the acceptable values based on other characteristics of the protected circuit 140 and the circuit designer typically selects the accepted values such that ESD protect circuit 130 will be in a nonconductive state during normal chip operation in the ground (zero) to VDD voltage range.